Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilayered schemes. These interconnect structures typically include copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared to aluminum-based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines are achieved in today's integrated circuit product chips by embedding the metal lines and vias in a dielectric material having a dielectric constant of less than silicon dioxide.
In the prior art, interconnect structures are typically fabricated utilizing lithography and etching to define the dimensions of the lines and vias. Photoresists and hard masks are typically used as a means to transfer a desired line and/or via pattern into an underlying dielectric material. As such, the dimensions of the line and/or via openings are limited to the resolution of the lithographic tool. Typically, the currently available 0.93 numerical aperture (NA) lithographic tool can only resolve lithographic patterns with openings of not less than 100 nm in diameter. Future generation of 1.2 NA lithographic tools are expected to print lithographic patterns with openings of about 70 to about 80 nm. Such large opening diameters contribute to undesirable low device density of the integrated circuit.
Moreover, as semiconductor device technology scales, interconnect wiring needs to scale accordingly. The current 45 nm node technology requires the M1-M4 (i.e., the first-fourth metal interconnect) lines to be 64 nm, and upcoming 32 nm node technology requires the same metal lines to be 45 nm, which is beyond the conventional lithographic capabilities as mentioned above.
Therefore, there is a need for reducing the diameters of the openings of the interconnect wiring structures to below the resolutions of the lithographic tools, i.e., there is a need for sub-lithographic feature patterning of interconnect structures for the 64 nm and 32 nm node generations.